Programme

Parameters characterizing safety critical systems are generally assigned very conservative values for reasons of safety assurance. The use of these values implies inefficient use of platform resources during run time. One approach to overcoming such conservatism is to go “Beyond Worst-Case Analysis” by using predictions to guide an algorithm. The algorithmic framework of algorithms using predictions offers a systematic approach to doing so.

We consider sporadic task system in the case when the period parameter of each task is characterized by a conservatively assigned value and a more optimistic (i.e., larger), but perhaps incorrect, prediction of this value.

We devise an algorithm that executes the system more efficiently during runtime if the prediction is correct, without compromising safety if it turns out to be incorrect.

In recent years, the usage of AI in embedded systems has exploded, including reliability- and safety-critical applications, where the effects of possible faults affecting the hardware cannot be neglected (e.g., in the automotive and aerospace domains). In all these cases, it is crucial first to estimate the probability that any fault may cause critical effects. Unfortunately, the complexity and size of the underlying hardware and of the executed software make it impractical to use traditional techniques, often based on fault injection (FI). For this reason, new solutions are required, combining clever statistical FI approaches with multi-level solutions, and suitable error models. Secondly, effective techniques to harden such systems and mitigate the effects of possible (transient and permanent) faults must be devised, acting on both the HW and the SW. This presentation summarizes the most recent contributions in this field by the CAD & Reliability Group within the Dept. of Control and Computer Engineering of Politecnico di Torino.

Managing access rights to physical and software resources in IT systems is a challenging task, as there is a need to represent in a meaningful, yet enforceable way, the conditions under which access to a resource by a subject should be allowed or denied. This task is particularly exacerbated when the decision point for these evaluations, it is placed in a constrained environment, such as a distributed architecture of embedded systems. In this presentation we will discuss how to manage complex and expressive access policies, expressed through the Attribute-Based Access Control (ABAC) paradigm, to manage access in a distributed system architecture, including low power and constrained devices. The presentation will briefly introduce the concept of dynamic access control or Usage Control, presenting a distributed version of the policy evaluation system to be introduced in a distributed smart home management architecture. Finally an integration with the ACE protocol for CoAP-based applications will be briefly discussed.

Artificial Intelligence is becoming pervasive in our daily operations especially due to the recent availability of LLMs and of Machine Learning (ML) algorithms that can perform classification (i.e., prediction of categorical labels) or regression (i.e., prediction of continuous numerical values). ML algorithms are typically expected to output very accurate predictions: this is the enabling condition for using ML in critical systems, where misclassifications may have cascading effects and have safety consequences for people, infrastructures, and the environment. However, this is only a part of a much more complex problem that is often overlooked: to be put into operation, software (and systems) have to undergo a rigorous certification process and prove compliance with safety standards. This typically involves estimating the probability of failure on demand, and exercising formal verification or stochastic modeling to prove that a specific component meets functional and non-functional requirements. This process aims at understanding how a software component behaves even when it faces unexpected inputs or operating conditions, to quantify its robustness to these potentially adverse events. Industrial standards such as the SOTIF (ISO/PAS 21448 – Safety Of The Intended Functionality) recognize performance limitations of ML-based software concerning inputs that belong to unsafe-unknown (e.g., samples out of training distribution) and unsafe-known, which are samples out of an Operational Design Domain (ODD). The ODD is an important concept in safety assessments as it defines the operating conditions (e.g. weather, time of the day, traffic congestion, etc.) for which a safety claim would apply, and thus the performance expected from a classifier in that ODD (more information in the PAS 1883:2020). Other white papers or standards offer different views, which are overall not very clear and lack precise guidelines for a practitioner or company that is willing to understand how to prepare an ML-based software component for certification. Therefore, this technical presentation will overview the existing proposals and pave the way for their application, presenting a simplified approach to the certification of ML-based software that lists the required items and the practical steps (and possible solutions) needed to deal with them.

The use of lightweight unmanned aerial vehicles (UAVs or drones) is expanding rapidly in both civilian and military applications. This growth necessitates enhanced safety and security measures in the software and hardware architectures that power these small embedded systems.

Currently, embedded drone systems often employ design choices suitable for low-power microcontrollers, yet these architectures offer limited safety and security capabilities.

This talk presents ongoing efforts by Minerva Systems and its partners to increase the robustness, safety, and security of such architectures using hardware capabilities on RISC-V (specifically CHERI RISC-V).

The focus will be on the widely adopted NuttX/PX4 software architecture for autonomous drone systems, discussing the challenges and strategies for deploying it on CHERI-enabled RISC-V cores.

Additionally, we will elaborate on our approach to implement hardware-based lightweight protection for independent flight applications and drivers.

The increasing spreading of small commercial unmanned aerial vehicles (UAVs, also known as drones) presents serious threats for critical areas, such as airports, power plants, and governmental and military facilities. In fact, such UAVs can easily disturb or jam radio communications, collide with other flying objects, perform espionage activity, and carry offensive payloads, e.g., weapons or explosives.

A central problem when designing surveillance solutions for the localization of unauthorized UAVs in critical areas is to decide how many triangulating sensors to use, and where to deploy them to optimize both coverage and cost effectiveness.

In this presentation, we show how to compute deployments of triangulating sensors for UAV localization, optimizing a given blend of metrics, namely: coverage under multiple sensing quality levels, cost-effectiveness, and fault-tolerance.

We focus on large, complex three-dimensional (3-D) regions, which exhibit obstacles (e.g., buildings), varying terrain elevation, different coverage priorities, and constraints on possible sensors placement. Our novel approach relies on computational geometry and statistical model checking and enables the effective use of off-the-shelf AI-based black-box optimizers. Moreover, our method allows us to compute a closed-form, analytical representation of the region uncovered by a sensor deployment, which provides the means for rigorous, formal certification of the quality of the latter.

We show the practical feasibility of our approach by computing optimal sensor deployments for UAV localization in two large, complex 3-D critical regions, the Rome Leonardo Da Vinci International Airport (FCO) and the Vienna International Center (VIC), using NOMAD as our state-of-the-art underlying optimization engine. Results show that we can compute optimal sensor deployments within a few hours on a standard workstation and within minutes on a small parallel infrastructure.

To be announced

Adversarial examples represent a serious threat for deep neural networks in several application domains. This work presents Carla-GeAR, a tool for automatically generating photo-realistic synthetic datasets related to driving scenarios that can be used for a systematic evaluation of the adversarial robustness of neural models against physical adversarial patches, as well as for comparing the performance of different adversarial defense/detection methods. The tool is built on the Carla simulator and allows the placement of adversarial patches crafted by state-of-the-art white box algorithms that can be attached to billboards or the back of a truck. All the code and the datasets generated are publicly available at https://carlagear.retis.santannapisa.it.

As distributed learning gains wider adoption across various sectors, identifying and mitigating new potential security risks becomes essential. This work presents novel black-box attacks specifically conceived for collaborative learning environments, where neural models could be partitioned between edge and cloud nodes. This ongoing investigation focuses on exploring new threat scenarios, paving the way for future research in secure AI.

The sensitivity of deep learning models to input perturbations poses serious concerns for the development of AI-powered safety-critical systems. This work presents a solution for improving the robustness of a neural network during training and evaluating its robustness at the cost of a single inference. The approach exploits the use of Lipschitz-bounded layers and provides some guidelines to support the user in selecting the best solution in a set of existing methods.

During the last decade, classification systems (CSs) received significant research attention, with new learning algorithms achieving high accuracy in various applications. However, their resource-intensive nature, in terms of hardware and computation time, poses new design challenges.

CSs exhibit inherent error resilience because of redundancy of training sets, and self-healing properties, making them suitable for Approximate Computing (AxC).

AxC enables efficient computation by using reduced precision or approximate values, leading to energy, time, and silicon area savings.

Exploiting AxC involves estimating the introduced error for each approximate variant found during a Design-Space Exploration (DSE). This estimation has to be both rapid and meaningful, considering a substantial number of test samples, which are utterly conflicting demands.

In our work, we investigate on sources of error resiliency of CSs, and we propose a technique to haste the DSE that reduces the computational time for error estimation by systematically reducing the test set. In particular, we cherry-pick samples that are likely to be more sensitive to approximation and perform accuracy-loss estimation just by exploiting such a sample subset. We integrate our technique into two different approaches for generating approximate CSs, showing an average speed-up up to ~18.

Graphics processing units (GPUs) are often employed to accelerate the inference of deep neural networks (DNNs) in cyber-physical systems to implement advanced perception and control functionalities. The typical GPU-accelerated DNN inference frameworks aim at maximizing the processing throughput rather than focusing on providing a predictable timing behavior, which is crucial for time-sensitive cyber-physical systems. This work proposes a framework for GPU-accelerated inference of DNNs on GPU-based embedded platforms, which provides enhanced timing predictability using a design-time optimization procedure of the DNN workload and a specialized method to schedule the GPU acceleration requests of the DNNs at runtime based on fixed-priority limited-preemptive scheduling. Fine-grained control of the inference is achieved by splitting the DNNs into smaller chunks, which are then scheduled using a specialized real-time scheduling mechanism. Experimental results on commercial-off-the-shelf (COTS) embedded platforms show significant improvements in terms of timing predictability when considering applications composed of multiple concurrent DNN acceleration requests.

With the growing adoption of cloud-based DNN execution, service providers face challenges in delivering high-quality service while maintaining cost-efficiency, especially under strict time constraints and multi-tenancy. Heterogeneous multi-accelerator systems offer promising solutions, but efficient scheduling is crucial. This paper introduces a low-overhead deep reinforcement learning algorithm for online DNN scheduling in multi-tenant environments. The proposed technique considers dataflow heterogeneity of accelerators and memory bandwidth contentions. It allows service providers to dynamically adapt scheduling policies for user requests, maximizing Service-Level-Agreement (SLA) satisfaction rates and hardware utilization. Our evaluation on a heterogeneous system composed of Simba and Eyeriss sub-accelerators demonstrates significant improvements compared to state-of-the-art techniques, with minimal energy overhead (less than 1.5%).

Convolutional Neural Networks (CNNs), have demonstrated remarkable performance across a range of domains, including computer vision and healthcare. However, they encounter challenges related to the increasing demands for resources and their susceptibility to adversarial attacks. Despite the significance of these challenges, they are often addressed independently in the scientific literature, which has led to conflicting findings.

In addressing the issue of resource demands, approaches have been developed which leverage the inherent error resilience of DNNs. The Approximate Computing (AxC) design paradigm reduces the resource requirements of DNNs by introducing controlled errors. With regard to the security domain, the objective is to develop precise adversarial attacks.

This paper introduces a novel technique for transferring adversarial attacks from CNN approximated through the AxC design paradigm (AxNNs), and other CNNs, regardless of their architecture and implementations. AxNNs are created by replacing components that require significant resources with approximate ones. Subsequently, adversarial attacks are generated targeting AxNNs and transferred to new CNNs.

The experimental results indicate that it is possible to transfer adversarial samples from an AxNN to target CNNs, especially whne the source AxNN has either a high accuracy, or an architecture that is deeper than the ones of the target CNNs.

This work presents a simulation framework developed on Unreal Engine 5 to create open datasets for perceptual tasks using synthetic images and point clouds. With respect to its predecessor, RailSim significantly enhances the realism of railway scenarios and supports several features to reflect real-world complexities: it gathers geo-referenced data and integrates them in the virtual environment, it simulates the movement of trains, vehicles, and pedestrians along predefined routes, it collects data from synthetic sensors and exports them into datasets for training and testing new perception and localization algorithms.

Early fault detection in automotive systems is critical for ensuring user safety and initiating corrective actions. This work proposes an Artificial Intelligence (AI) framework for automotive fault detection. The system monitors Hardware Performance Monitor (HPM) counters to identify anomalous behavior and trigger alerts. By evaluating various fault detection models, the study identifies a neural network-based approach achieving a high detection accuracy of 96%. The impact of inference latency on overall system performance is also assessed.

Bringing an existing codebase into MISRA compliance is known to be a difficult, risky and time-consuming task. Yet, when a product needs a functional safety certification and rewriting the software is out of question, this is a necessity. Such an endeavor requires facing multiple tradeoffs and, consequently, lots of experience both on the codebase and on MISRA. The choices between deviating the guideline, and the (often, many) ways in which code may be changed and deviations may be formulated, are tough and with consequences that are not immediately evident. While, clearly, a project undertaking MISRA compliance at a late development stage is likely to rely on deviations more than other projects, one should take into account the interdependence among MISRA guidelines and that such deviations have to be rock-solid (as they will inevitably catch the assessors' attention).

In this presentation, we illustrate our experience and the several lessons learned while undertaking MISRA compliance work in several projects. This includes closed-source projects (which cannot be disclosed for confidentiality reasons) as well as open-source projects, most notably the Zephyr RTOS and the Xen hypervisor, both used in many embedded systems.

Real-time object detection systems play a crucial role in different fields like autonomous driving, robotics, and healthcare, where efficiency, performance, and accuracy are paramount. These systems can be categorized into soft and hard real-time based on their need for precise and timely responses. Recent advancements, particularly in Convolutional Neural Networks (CNNs), have markedly enhanced object detection models, ensuring reliable real-time performance. FPGAs stand out by offering low as well as deterministic latency and high throughput, making them ideal platforms for these applications.

We review existing FPGA-based real-time object detection literature, highlighting prevalent detection algorithms, acceleration techniques, and optimization strategies. We also examine evaluation metrics and datasets typically used to assess these systems. The presentation will provide insights into state-of-the-art FPGA implementations, including a comparative analysis, challenges faced, and future research directions. This review aims to guide researchers and practitioners in leveraging FPGA technology to develop advanced real-time object detection in embedded systems.

Neuromorphic Computing aims to emulate the processes involved in the natural structure of biological neurons. To this end, brain-inspired systems are being developed that aim to mimic the human brain's intrinsic ability to process and learn from massive amounts of data with a very limited power budget.

Traditional ANNs have evolved into what are now called Spiking Neural Networks (SNNs), which bring more biological plausibility to machine learning applications, depending on the neural and synaptic models implemented.

SNNs find their best application in dedicated hardware, where energy efficiency and high levels of parallelism of operations can be maximally optimized. Besides the use of innovative devices such as memristors, dedicated digital HW design of SNN accelerators is one of the preferred ways to develop neuromorphic architectures: many research efforts are directed towards the creation of custom silicon chips to simulate SNNs, while others prefer to resort to FPGA design, which is also less expensive, to take advantage of its reconfigurability.

Although SNN accelerators provide a highly specific and thus task-focused set of operations, they cannot operate as stand-alone systems, but require external control and configuration. This can be achieved by integrating the accelerators into complete heterogeneous systems with a main controller unit that manages the operations via a dedicated data bus.

In this contribution, we present the configuration of ReckOn, an open-source recurrent SNN accelerator implemented on a Xilinx FPGA, performed by the ARM controller of the Xilinx Zynq chip through the AXI bus, thanks to the extensive set of features offered by the Xilinx memory-mapped IPs. By using an AXI master peripheral, we manage to control the operations of the accelerator through: (1) an AXI-SPI bridge used to configure the SNN, (2) an AXI-BRAM bridge used to cache the spiking data packets sent for learning or inference, and (3) an AXI-controlled GPIO peripheral used to communicate with the FSM-based AER data encoder.

The presented architecture allows the use of neuromorphic hardware, otherwise only available via taped-out ASIC, and has also been validated by reproducing the binary classification use case provided with the source code.

L'applicazione di algoritmi di Image Processing comporta il superamento di una serie di sfide tecnologiche, architetturali e implementative. MBDA Italia, tenendo conto di questi vincoli, ha intrapreso uno studio sistematico di algoritmi noti in letteratura volti all’acquisizione di nuove competenze in materia, applicandoli in un algoritmo complessivo che permetta l’individuazione e tracciamento di un target in una sequenza video. In questo modo è stato possibile ottimizzare la parallelizzazione e comparare soluzioni basate su CPU e FPGA dal punto di vista delle performances su due evaluation board e dimostrare la fattibilità in sistemi real time usati nella difesa.