Programme

Abstract

Railway interlocking systems traditionally rely on extensive wired infrastructures, leading to high costs, limited flexibility, and significant deployment and maintenance challenges. Recent advances in wireless communications and the Smart Wayside Object Controller (SWOC) concept have enabled the evolution toward wireless railway interlocking systems. This paper presents a feasibility study on the adoption of wireless interlocking for Italian railways, relying on an infrastructure that is currently being developed by Rete Ferroviaria Italiana (RFI). The paper first reviews the Shift2Rail (S2R) initiative and the main technological challenges associated with wireless railway interlocking. Then, it overviews the existing RFI system and discusses possible solutions toward wireless interlocking, considering architectural evolution, safety communication protocols, and candidate wireless technologies. Our analysis shows that wireless interlocking is technically feasible, although several challenges related to safety, communication performance, and system integration still remain open. Future work will focus on the design and implementation of a demonstrator to support the experimental assessment of the proposed wireless interlocking solutions.

Abstract

Artificial Intelligence (AI) is increasingly being integrated into modern Safety-Critical systems running AI algorithms, such as lightweight Convolutional Neural Networks (CNNs), which enable a wide range of autonomous functionalities, including object recognition, scene understanding, trajectory prediction, and decision making.

Recent advances in semiconductor technologies have further accelerated this trend by enabling the integration of dedicated AI accelerators directly within autonomous control platforms (i.e., at the edge), which reduces the CNN response latency. Nevertheless, the scaling of technology nodes toward 7 nm and below makes edge devices increasingly vulnerable to hardware reliability issues (caused for example by manufacturing defects and premature device degradation), which may ultimately manifest as Soft Errors at the application level, silently corrupting intermediate computations. Such faults can alter internal activations, and modify the final CNN output during inference, resulting in incorrect control decisions, or even catastrophic accidents involving human lives. Therefore, effective application-level monitoring mechanisms are required to promptly identify anomalous NN behavior, meeting the resource constraints while enabling the activation of recovery strategies before the fault causes severe consequences.

Although existing solutions demonstrated promising results in detecting faults, they generally analyze each inference independently, treating each NN inference as an isolated event, which, in real-world deployments, neglects the sequential nature of the sensory observations processed by the autonomous system.

Indeed, in real deployments, CNN process sequential input observations (i.e., images), often producing repeated outcomes over time. This work introduces a fault detection mechanism that, at each inference, evaluates both current and recent outcomes within a time window to determine the presence of faults.

Specifically, the proposed detection mechanism relies on an auxiliary lightweight Multi-Layer Perceptron (MLP) trained to replicate the same behavior of the reference CNN model by processing statistical measurements computed on the output of the first convolutional layer. During the operational phase, both neural networks (the original one and the MLP operate in parallel) produce inference results that are later used to compute the level of agreement. Such an agreement is calculated by comparing the inference outcomes across the time window of observations. In the end, a fault is detected when the level of agreement between the MLP and the main CNN drops under a predefined threshold.

It is worth noting that the proposed method requires no hardware changes and can be deployed on pre-trained models, and it can be trained through knowledge distillation. Moreover, the experimental results gathered on a set of representative CNNs and datasets show that the detection system maintains a false positive rate of no more than 7.33%, and additionally, it can correctly identify faulty cases up to 97.79%.

Abstract

Modern cyberattacks, including Advanced Persistent Threats (APTs), are typically multi-stage campaigns that exploit multiple vulnerabilities and weaknesses over extended periods to compromise networked systems. Embedded systems, which increasingly operate as components of larger Operational Technology (OT) environments, are particularly exposed to such threats due to their long lifecycles, resource constraints, heterogeneous architectures, and stringent availability requirements. Traditional Intrusion Detection Systems (IDSs) remain a widely adopted defense mechanism; however, they generally focus on detecting isolated malicious events. As a result, they are often ill-suited to identifying multi-step, low-and-slow attacks that unfold across time and involve multiple assets and attack stages. The lack of effective alert-correlation capabilities also contributes to large volumes of alerts, many of which are false positives, resulting in alert fatigue and limiting the ability of defenders to understand the evolution and impact of an intrusion.

Attack Scenario Reconstruction addresses these limitations by correlating heterogeneous security alerts and constructing a chronological representation of an attack. This enables defenders to navigate complex security information, identify how an asset was compromised, reconstruct the progression of an intrusion, and support faster and more effective response actions.

In this work, we provide a deployment-oriented analysis of state-of-the-art attack scenario reconstruction approaches, identifying their main stages, architectural characteristics, and limitations in real-world embedded and OT environments. Based on this analysis, we identify key research and deployment gaps and present a reconstruction methodology and framework designed to address them. Unlike existing approaches, our framework operates directly on raw network flows, enabling a more comprehensive and context-aware reconstruction process while providing greater control over alert generation and alert semantics. The framework employs machine-learning-based techniques to generate security alerts and a graph-based correlation approach to model relationships among events and attack stages, an aspect that remains insufficiently addressed in the current state of the art. By combining flow-level analysis, alert generation, and graph-based correlation, our approach aims to improve the interpretability, contextualization, and operational usability of attack reconstruction for embedded systems deployed within complex OT environments.

Abstract

Digital Twins rely on continuous data exchange with physical systems in order to maintain an accurate and timely representation of the real-world environment. Achieving low communication latency is therefore a critical requirement for many Digital Twin applications, particularly in IoT scenarios where near-real-time monitoring and control are required. While many researches focus on optimizing network infrastructures or deploying Digital Twin components closer to the edge, less attention has been given to the internal architecture of the Digital Twin middleware itself. In this paper we investigate the performance of the MQTT DataBridge component of the Eclipse BaSyx Asset Administration Shell framework. In particular, the authors analyze the latency behavior under different deployment configurations, comparing a traditional mono-instance deployment with alternative multi-instance containerized configurations. The experiments evaluate latency across varying numbers of Digital Twin instances, message sizes, and CPU constraints. Results show that shared multi-instance deployments significantly reduce latency compared to the standard mono-instance configuration under moderate loads. However, the advantage diminishes as the number of instances increases beyond certain thresholds, revealing important scalability trade-offs. These findings highlight the impact of middleware deployment strategies on Digital Twin communication performance and provide guidelines for optimizing Asset Administration Shell-based Digital Twin infrastructures.

Abstract

The growing complexity of cyber-physical systems (CPSs) calls for early prototyping tools that combine accuracy, speed, and usability. Virtual Platforms (VPs) provide fast functional simulation, but hybrid co-emulation solutions, in which key digital components are deployed on FPGA, become necessary when accurate timing modelling is required and RTL simulation is too costly. However, existing hybrid emulation tools are mostly proprietary, and rely on vendor-specific FPGA features. To address this gap, we introduce an open-source framework that connects SystemC-based VPs with FPGA emulation, enabling full-system co-emulation of digital and non-digital components. The FPGA accelerates the execution of main digital subsystems, while a wrapper coordinates timing and communication with the VP through JTAG, maintaining synchronization with simulated peripherals. Evaluations using a RISC-V SoC, with an example in the biosignals processing domain, show up to 2500x speedup compared to RTL simulation, while maintaining less than 2x total simulation time relative to pure FPGA emulation.

Abstract

Modern embedded systems are typically based on a parallel heterogeneous HW/SW architecture. This implies a very complex design, considering the number of variables to be traded off. Thus, it is necessary to adopt System-Level HW/SW co-design methodologies to design these systems.

However, to be both effective and efficient, a parallel heterogeneous architecture must fully exploit the potential degree of concurrency available in the system behavior. Consequently, the corresponding co-design methodology must be capable of identifying, evaluating, and properly managing potential concurrency from the earliest stages of the design flow.

Toward this goal, this work presents an extension of an existing system-level HW/SW co-simulator, part of the HEPSYCODE methodology, to perform system-level concurrency analysis on CSP-like system-level behavioral models. The proposed approach allows to evaluate system-level concurrency metrics to be provided as input to a Design Space Exploration (DSE) step to fully exploit the parallel nature of the target architecture.

Abstract

Modern embedded systems are commonly based on heterogeneous parallel HW/SW architectures, which demand a complex design process involving many variables and trade-offs. Thus, traditional design methodologies are no longer suitable, and the adoption of System-Level HW/SW co-design ones is increasingly needed.

However, when a target architecture provides also the possibility to reconfigure part of the HW at run-time, incorporating the exploitation of this capability into an HW/SW co-design methodology introduces additional challenges that must be carefully addressed within the co-design flow. The proposed approach aims to extend an existing co-design methodology, called HEPSYCODE, with the ability to suggest different system configurations, accounting for HW reconfiguration at run-time, and its relative cost. In particular, this work focuses on the extensions applied to the corresponding system-level HW/SW co-simulator in order to evaluate the quality of such configurations.

Abstract

Modern real-time embedded systems increasingly rely on runtime reconfigurable architectures to minimize size, weight, and power consumption while preserving timing predictability. However, reconfiguration delay is non-negligible and tends to fluctuate due to contention over shared resources. Unlike existing solutions, which impact system resources or timing behavior, this work introduces an approach and accompanying tools to establish a safe and tight upper bound on reconfiguration delay by accurately modeling resource contention, with no additional resource overhead, applicable to the vast majority of embedded Systems-on-Chip. Furthermore, by leveraging Quality-of-Service mechanisms offered by modern Systems-on-Chip, the proposed approach enables designers to enforce a maximum threshold for reconfiguration delay and preserve it in the presence of interference from concurrently running tasks. To validate the proposed approach, two experiments are conducted on a representative configuration on a Xilinx Zynq UltraScale+ platform. Experimental results confirm that the reconfiguration delay bound holds under induced worst-case interference scenarios, showing that, under heavy workload conditions, the reconfiguration delay can reach up to 6.3 times its value in isolation. Moreover, the approach can automatically generate a Quality-of-Service configuration that enforces a maximum reconfiguration delay of 1.8 times its value in isolation, with only a 14% performance degradation on contending tasks and no extra resource consumption, outperforming current state-of-the-art solutions.

Abstract

WebAssembly is emerging as a portable, sandboxed runtime for edge and IoT deployments. On microcontrollers, the runtime cost of those guarantees remains poorly understood. Prior work measures end-to-end execution time, treating the interpreter as a black box and providing no insight into where cycles are spent.

We present a cycle-accurate, per-opcode and per-phase characterization of the WAMR fast interpreter across two MCU platforms spanning two ISAs. Profiling on real hardware reveals that interpretation overhead ranges from 14.5× to 30.5× relative to native execution, with the dominant cost source depending on workload structure: memory instructions dominate memory-intensive benchmarks, while control-flow handlers (call, return) dominate workloads with frequent function invocations in compute-intensive benchmarks. A per-phase breakdown on a simulated platform shows that software bounds checking accounts for 36-60% of memory handler cost, and that, for simple ALU handlers, the decode phase exceeds both the operation itself and the dispatch overhead targeted by prior work. Further analysis uncovers a non-local register pressure effect that amplifies the bounds-check cost across the entire interpreter function. We design a minimal hardware extension that targets both effects simultaneously, reducing total benchmark execution.

Abstract

The increasing heterogeneity of IoT devices across Cloud-Edge Continuum architectures calls for unified orchestration, hardware-agnostic execution, and seamless workload mobility over nodes spanning from high-performance microprocessors down to resource-constrained MCUs. This work introduces a distributed hypervisor for I/O virtualization on MCU-based IoT devices, in which cooperating per-node instances share peripheral access through a DDS-based middleware, laying the groundwork for fully autonomous distributed orchestration across the Cloud-to-Things continuum. Each hypervisor instance runs on top of Zephyr RTOS, hosts applications as WebAssembly modules executed by the WAMR runtime, and exposes a unified peripheral API through which hardware access is resolved either locally or transparently on remote nodes. Beyond portability, the proposed architecture supports live application migration: the full application state is captured on the source node and restored on the destination one, allowing stateful workloads to be relocated across heterogeneous MCU architectures while preserving transparent access to remote peripherals. A Kubernetes-based cloud orchestrator governs node registration, application deployment, and migration decisions along the continuum. The approach is validated through two proof-of-concept scenarios: in the first, a GPIO pin is remotely toggled across two heterogeneous MCU architectures; in the second, a running application is migrated between nodes with its state fully preserved. A performance evaluation quantifies the overhead introduced by the WASM runtime, the DDS communication stack, and the migration process, establishing a baseline for future optimization work.

Abstract

Optimising code for embedded systems is essential to meet strict demands on speed, memory, energy, and determinism. Such optimisation has traditionally relied on expert developers, but large language models (LLMs) are now emerging to automate code generation and improvement. This presentation compares the optimisations produced by leading LLMs with those of a rule-based tool developed by STMicroelectronics, driven by human-defined rules recognised in the research community. Using a custom bare-metal platform for pure embedded execution and a FreeRTOS variant with a priority-preemptive, soft-real-time task layout targeting a real-world case, we evaluate eighteen contemporary open-weight and frontier proprietary LLMs on ARM Cortex-M microcontrollers across three benchmarks of increasing scope (a micro-benchmark, an N-Body macro-benchmark, and a GNSS workload), two boards, and five compiler optimisation levels. Each model optimises through iterative refinement driven by compilation, correctness, and performance feedback. Our findings revise earlier conclusions: On the compute- bound N-Body benchmark most frontier models reduce cycles by roughly 96%, on par with the expert tool (95%), and on the micro-benchmark they surpass it in both speed and energy. This competitiveness is uneven: results on the real-world GNSS workload are bimodal and device-dependent, and the expert tool retains a clear lead under FreeRTOS. Frontier models largely produce compilable, architecturally sound code, often on the first attempt; iterative refinement, applied where they fall short, helps on simpler benchmarks but yields diminishing and on the complex GNSS workload, negative returns, at times regressing correctness.

Abstract

Artificial intelligence is increasingly being integrated into cyber-physical and safety-critical systems, creating the need for computing platforms capable of delivering both high performance and predictable timing behavior. Traditional AI accelerators have largely been optimized for throughput and energy efficiency, often making timing analysis and schedulability assessment difficult. In response, a new generation of tiled and spatial accelerator architectures is emerging, combining distributed processing elements, local memories, and explicit communication mechanisms to improve scalability and offer greater temporal predictability.

This presentation discusses the role of tiled AI accelerators in real-time systems and examines the architectural features that can support both efficient and predictable AI inference. Particular attention is devoted to aspects such as distributed memories, explicit data movement, deterministic communication, resource allocation, and resource contention.

The AMD AI Engine architecture is used as a representative case study to illustrate design choices that influence both performance and timing predictability. The paper aims to highlight key challenges, opportunities, and research directions for the adoption of tiled AI accelerators in future real-time and safety-critical systems.

Abstract

Second fermentation in bottle is a critical step in sparkling wine production, where pressure and carbon dioxide evolution directly affect product quality and safety. Conventional aphrometers offer limited process visibility due to single-point measurements. This work presents a connected aphrometer developed within the EdgeAI-TRUST project, based on the STM32WL5M platform with LoRa connectivity, enabling real-time pressure monitoring and edge-based analytics. By combining Bayesian hierarchical modeling and machine learning, the system forecasts fermentation dynamics and detects abnormal patterns at an early stage. This approach improves process observability, traceability, and predictive control in sparkling wine production.

Abstract

This presentation illustrates the current status and perspectives of the initiative “Manifesto on Embedded Systems and Smart Manufacturing,” promoted as a joint effort by the CINI National Laboratory on Embedded Systems and Smart Manufacturing. The manifesto, which has already been publicly disseminated through media channels and discussed within the IWES community, argues that digital and technological sovereignty should encompass more than semiconductor production, cloud infrastructure, or artificial intelligence alone. Rather, it depends on the ability to design, integrate, validate, and deploy complete embedded and cyber-physical systems that bring reliable, secure, sustainable, and interoperable intelligence into real industrial processes.

The central focus is the strategic role of embedded systems as the layer where hardware, software, data, AI models, communication, real-time constraints, safety, security, energy efficiency, and certification converge into operational behavior. From this perspective, smart manufacturing is not merely the adoption of additional sensors or dashboards, but the coordinated evolution of factories, machines, operators, digital twins, edge-cloud infrastructures, and industrial data spaces into trustworthy cyber-physical ecosystems.

The manifesto aims to engage a broader stakeholder community and currently includes more than 100 scientists from Italy and several European countries involved in embedded systems research and innovation. Its goal is to connect academic competences, industrial needs, demonstrators, open technologies, standardization efforts, and advanced training, with particular attention to Italy’s role as a manufacturing country. By framing embedded systems and smart manufacturing as strategic national infrastructure, the manifesto aims to stimulate collaboration among research groups, industry, and institutions, and to identify shared priorities for the next generation of intelligent distributed systems.

Abstract

Decision trees (DTs) are attractive for edge computing for their interpretability and low computational cost. However, DT inference is usually implemented as a sequential, data-dependent traversal from root to leaf, causing unpredictable branching and irregular memory accesses on microcontrollers. This becomes critical in online inference, where sensor samples arrive continuously and must be classified within strict latency and energy budgets.

We present SNAP (Speculative Node Anticipation Process), a DT traversal kernel for online inference at the edge. SNAP turns the traversal into a speculative process: it selects a candidate root-to-leaf path and evaluates its split predicates in parallel using vector extensions, achieving up to 59.92% lower inference latency than a state-of-the-art scalar baseline on an ARM Cortex-M55 MCU with ARM Helium.

Abstract

Embedded deep neural networks (DNNs) are increasingly deployed in reliability-sensitive domains such as aerospace, autonomous systems, industrial control, and edge sensing, where hardware-level faults such as single-event upsets (SEUs) can compromise inference correctness. Existing SEU-resilient training strategies often optimize different robustness objectives and therefore occupy competing points in the accuracy–resilience design space. This work investigates evolutionary model merging as a way to combine the benefits of such strategies. Two parent DNNs sharing the same architecture are trained using distinct and competing SEU-resilience objectives. An evolutionary search is then used to discover model-merging recipes that combine the parent networks into a new candidate model. The underlying hypothesis is that such combinations may move the resulting DNN toward a flatter region of the solution landscape, making its inference behavior less sensitive to SEU-induced perturbations. The merged DNNs are evaluated through SEU fault injection and compared against both parent models using shared accuracy and reliability metrics. The goal is to determine whether automated model composition can produce embedded DNNs that inherit complementary resilience properties and potentially outperform the individual training strategies, while preserving the original inference architecture and remaining independent of a specific hardware target.

Abstract

The advent and widespread adoption of Deep Learning, Agentic-AI and Large Language Models (LLMs) are redefining computing paradigms, shifting the epicenter of computation from the Edge to the Cloud, where the processing power required for applications leveraging these technologies resides. As these applications become increasingly pervasive, assisting humans across an ever-growing and diverse range of contexts and situations, the demands for processing power, memory, and energy to run the underlying systems are also rising, raising concerns about the long-term sustainability of this approach. Indeed, while Artificial Intelligence (AI) has become a cornerstone technology for intelligent systems, its ability to solve highly complex problems comes at the cost of significant energy consumption; furthermore, for many tasks, humans still outperform machines and, crucially, operate far more efficiently (the human brain consumes an average of 20 W). In such a context, neuromorphic computing emerges as an innovative paradigm that draws inspiration from biological systems to offer solutions designed to combine low energy consumption with high performance. The primary computational model employed in neuromorphic computing is the Spiking Neural Network (SNN), which more faithfully replicates the behavior of biological neurons and the way they utilize discrete pulses, known as spikes, to communicate with one another. By implementing neural and synaptic computation via spike-driven communication, SNNs enable energy-efficient systems that exploit time as an intrinsic, additional input dimension. In this sense, unlike traditional systems, neuromorphic computing makes use of non-volatile memory components and analog processing circuits that allow them to process more information while reducing power consumption. Within this landscape, the physical substrate on which SNNs are deployed plays a decisive role in determining the actual energy and performance gains that can be achieved. While dedicated neuromorphic chips and analog implementations promise the highest efficiency, Field-Programmable Gate Arrays (FPGAs) represent a particularly attractive middle ground: they combine hardware-level parallelism and reconfigurability with short design cycles, low development cost, and a power envelope well below that of general-purpose CPUs and GPUs, making them especially suited to the rapid prototyping and edge deployment of spiking architectures. In such a context, the Leaky Integrate-and-Fire (LIF) neuron constitutes the fundamental building block of most SNNs, striking a favorable balance between biological plausibility and computational simplicity. We present the design and hardware implementation of a LIF neuron model on a Xilinx Zynq UltraScale+ FPGA. The membrane dynamics are discretized through a forward-Euler scheme and realized with fixed-point arithmetic, so as to avoid the overhead of floating-point units while preserving numerical accuracy and minimizing resource occupation. The resulting module is parameterizable and modular, enabling its replication and time-multiplexing to compose larger neural layers, and it communicates through an event-driven spike interface that exploits the intrinsic sparsity of spike-based computation. The proposed implementation is evaluated in terms of hardware resource utilization, maximum operating frequency, and the per-update latency and throughput of the neuron datapath (i.e., the number of clock cycles required to update the membrane potential and emit a spike), with particular emphasis on power consumption and energy per spike. The obtained results, albeit preliminary, demonstrate that FPGA-based LIF neuron can be considered a practical and scalable building block toward sustainable, low-power neuromorphic accelerators for edge intelligence.

Abstract

Model-based formal verification of industry-relevant Cyber-Physical Systems (CPSs) is often a computationally prohibitive task. In most cases, the complexity of the models precludes any prospect of symbolic analysis, leaving numerical simulation as the only viable option. Unfortunately, exhaustive simulation of a CPS model over the entire set of plausible operational scenarios is rarely possible in practice, and alternative strategies such as Statistical Model Checking (SMC) must be used instead.

In this presentation, we show that the number of model simulations (samples) required by SMC techniques to converge can be significantly reduced by considering multiple (an ensemble of) Adaptive Stopping Algorithms (SAs) at once, and that the simulations themselves (by far the most expensive step of the entire workload) can be efficiently sped up by exploiting massively parallel platforms.

With three industry-scale CPS models, we experimentally show that the use of an ensemble of two state-of-the-art SAs (AA and EBGStop) may require dozens of millions fewer samples when compared to running a single algorithm, with reductions in sample size of up to 78%. Furthermore, we show that our implementation, by massively parallelizing system model simulations on a HPC infrastructure, yields speed-ups for the completion time of the verification tasks which are practically linear with respect to the number of computational nodes, thus achieving an efficiency of virtually 100%, even on very large platforms. This makes it possible to complete tasks of model-based SMC verification for complex CPSs in a matter of hours or days, whereas a naïve sequential execution would require from months to many years.

Abstract

Graphics Processing Units (GPUs) are increasingly employed as accelerators in embedded systems to meet stringent performance and energy constraints. However, efficient resource management is essential to achieving predictable execution and maximizing hardware utilization. To this end, partitioning is often employed as a technique to enhance performance consistency and resource efficiency.

This talk presents an analysis of the NVIDIA GPU partitioning methodology: Green Context, an officially supported API maintained by NVIDIA.

The analysis is structured in two phases. First, we evaluate key design-level aspects, including ease of integration into embedded environments, compatibility with constrained hardware/software ecosystems, and overhead implications. Second, we perform an extensive experimental evaluation, analyzing execution time and performance variability under different kernel characteristics. We further

assess the method in contention-based scenarios to determine its suitability for real-time and latency-sensitive applications.

Our findings provide insights into whether or not partitioning should be used, depending on application characteristics and the trade-offs between baseline and search-based partitioning strategies,

guiding the choice of using GPU management techniques in embedded computing.