Presentation title

Preemptable Partial Reconfiguration for Real-Time Computing with FPGAs

Authors

Enrico Rossi and Giorgio Buttazzo

Institution(s)

Scuola Superiore Sant’Anna

Presentation type

Technical presentation

Abstract

This work presents the implementation of a preemptable reconfiguration interface that can be used in real-time embedded systems exploiting FPGA accelerators. The approach is based on a custom reconfiguration controller that allows to interrupt and resume a partial reconfiguration process. Such a controller guarantees worst-case latency bounds on its operations, so allowing the use of response-time analysis techniques to determine the finish time of preemptable reconfigurations under real-time constraints.

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Additional material

• Presentation slides: [pdf]

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