Presentation title

DPR time estimation: a static timing approach

Authors

Giacomo Valente, Gabriella D'Andrea, Tania Di Mascio and Luigi Pomante

Institution(s)

University of L'Aquila

Presentation type

Presentation of a research group from one or more scientific institutions

Abstract

Modern Field-Programmable Gate Arrays offer Dynamic Partial Reconfiguration (DPR) capabilities, a characteristic that opens new scheduling opportunities for real-time applications running on heterogeneous platforms. To evaluate when it is really useful to exploit a DPR, in this work we present the characterization of its reconfiguration cost in terms of time. To obtain such results, the components involved in a DPR process have been identified and an innovative approach to calculate the DPR time and its worst-case bound is provided. We validate our approach on real DPR-compliant platforms, showing that our proposal is general enough to be applied to modern DPR-compliant platforms.

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Additional material

• Presentation slides: [pdf]