Presentation title
Memory management strategies in real time embedded autonomous systemsAuthors
Gianluca Brilli, Alessandro Capotondi, Paolo Burgio and Andrea MarongiuInstitution(s)
University of Modena e Reggio EmiliaPresentation type
Presentation of a research group from one or more scientific institutionsAbstract
The new generation heterogeneous System-on-Chips (HeSoCs) represent a valid option for the realization of autonomous systems, in particular in the field of autonomous driving, autonomous flight and industry 4.0. These systems represent the perfect candidates to handle heavy computational loads, in which the sequential computation, typically performed by a processor with a reduced number of cores, must necessarily be combined with a dedicated co-processor to deal with a specic problem, typically characterized by a high degree of parallelism. Examples of these systems are the novel embedded GPGPUs or FPGA based systems. Convolutional Neural Networks or modern mapping and localization algorithms that can be found inside an autonomous robot are typical workloads for this type of system. However, by construction these SoCs suffer from various problems, which could affect their applicability in Real-Time contexts, where it is necessary that a certain task never exceed a critical time threshold (deadline). I will discuss one of the main problems that affects these types of systems: the memory interference phenomenon to which a task is subject, when there are more than one Hardware or Software tasks within the system that try to access the main memory (DRAM) simultaneously. Finally, I will try to outline some strategies undertaken from the point of view of the regulation of the memory bandwidth available by the components within a heterogeneous System-on-Chip. The idea behind this research is to model a DMA hardware access policy, capable of reducing the granularity of copy requests and serving them through a fair methodology.
Additional material
- Presentation slides: [pdf]